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ISL6540A
Data Sheet March 12, 2007 FN6288.2
Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability
The ISL6540A is an improved version of the ISL6540 single-phase voltage-mode PWM controller with input voltage feedforward compensation to maintain a constant loop gain for optimal transient response, especially for applications with a wide input voltage range. Its integrated high speed synchronous rectified MOSFET drivers and other sophisticated features provide complete control and protection for a DC/DC converter with minimum external components, resulting in minimum cost and less engineering design efforts. The output voltage of the converter can be precisely regulated with an internal reference voltage of 0.591V, and has an improved system tolerance of 0.68% over commercial temperature and line load variations. An external voltage can be used in place of the internal reference for voltage tracking/DDR applications. The ISL6540A has an internal linear regulator or external linear regulator drive options for applications with only a single supply rail. The internal oscillator is adjustable from 250kHz to 2MHz. The integrated voltage margining, programmable pre-biased soft-start, differential remote sensing amplifier, and programmable input voltage POR features enhance the ISL6540A value.
Features
* VIN and Power Rail Operation from +3.3V to +20V * Fast Transient Response - 0 to 100% Duty Cycle - 15MHz Bandwidth Error Amplifier with 6V/s Slew Rate - Voltage-Mode PWM Leading and Trailing-Edge Modulation Control - Input Voltage Feedforward Compensation * 2.9V to 5.5V High Speed 2A/4A MOSFET Gate Drivers - Tri-state for Power Stage Shutdown * Internal Linear Regulator (LR) - 5.5V Bias from VIN * External LR Drive for Optimal Thermal Performance * Voltage Margining with Independently Adjustable Upper and Lower Settings for System Stress Testing & Over Clocking * Reference Voltage I/O for DDR/Tracking Applications * Improved 0.591V Internal Reference with Buffered Output - 0.68%/1.0% Over Commercial/Industrial Range * Source and Sink Overcurrent Protections - Low- and High-Side MOSFET rDS(ON) Sensing * Overvoltage and Undervoltage Protections * Small Converter Size - QFN package * Oscillator Programmable from 250kHz to 2MHz * Differential Remote Voltage Sensing with Unity Gain * Programmable Soft-Start with Pre-Biased Load Capability * Power Good Indication with Programmable Delay * EN Input with Voltage Monitoring Capability * Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL6540A (28 LD 5x5 QFN) TOP VIEW
VMON COMP HSOC LSOC GND
Applications
* Power Supply for some Microprocessors and GPUs * Wide and Narrow Input Voltage Range Buck Regulators * Point of Load Applications * Low-Voltage and High Current Distributed Power Supplies
21 20 19 BOOT UGATE PHASE PGND LGATE PVCC LINDRV
FB
28 VSEN+ VSENREFOUT REFIN SS OFS+ OFS1 2 3
27
26
25
24
FS
23
22
Ordering Information
PART NUMBER* (Note) ISL6540ACRZ PART MARKING TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. #
GND 4 5 6 7 8 VCC 9 MARCTRL 10 PG_DLY 11 PG 12 EN 13 VFF 14 VIN BOTTOM SIDE PAD 18 17 16 15
ISL6540ACRZ 0 to +70 28 Ld 5x5 QFN L28.5x5
ISL6540ACRZA ISL6540ACRZ 0 to +70 28 Ld 5x5 QFN L28.5x5 ISL6540AIRZ ISL6540AIRZ -40 to +85 28 Ld 5x5 QFN L28.5x5 -40 to +85 28 Ld 5x5 QFN L28.5x5
ISL6540AIRZA ISL6540AIRZ *Add "-T" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EN VIN LIN_DRV
VCC
POWER-ON REFERENCE VREF = 0.591 V RESET (POR) INTERNAL SERIES LINEAR EXTERNAL SERIES LINEAR DRIVER HSOC
Block Diagram
REFIN
2
VOLTAGE MARGINING SOURCE OCP OTA SOFT-START AND FAULT LOGIC PWM COMP EA GATE CONTROL LOGIC OV/UV COMP SOURCE OCP OSCILLATOR PGOOD COMP G = -1 100A SINKING OCP VMON PG_DLY PG LSOC VFF FS
REFOUT 100A
MAR_CTRL BOOT
OFS+
OFS-
UGATE
SS
PHASE
ISL6540A
FB
COMP PVCC
VCC
1.8V
LGATE
PGND
VSEN+
GND GND
VSEN-
G=1 UNITY GAIN DIFF AMP
FN6288.2 March 12, 2007
ISL6540A Typical Application I (Internal Linear Regulator with Remote Sense)
+3.3V to +20V RCC RVIN LIN CF2 CF1 VCC RVFF VIN VFF CF3 CVFF CHSOC UGATE VCC EN REFIN REFOUT PG CPG_DLY PG_DLY FS PHASE CHFOUT LGATE PGND Q2 RLSOC 10 10 CBOUT Q1 LOUT VOUT Internal 5.6V Bias Linear Regulator PVCC BOOT HSOC RHSOC CBOOT RBOOT DBOOT CHFIN CBIN
ISL6540A
LSOC
RFS
CLSOC COMP C2 C1 ZFB R2 FB R1
C3
R3 ZIN
MARCTRL ROFS+ OFS+ RMARG ROFSOFS-
VMON VSEN+ CSEN ROS VSENLINDRV GND GND VSENSERFB VSENSE+
SS CSS
3
FN6288.2 March 12, 2007
ISL6540A Typical Application II (External Linear Regulator without Remote Sense)
+3.3V to +20V LIN CF2 CLC RLC RVIN LINDRV CF3 RVFF CVFF VCC VIN VFF REFOUT REFIN EN PG CPG_DLY PG_DLY FS COMP PHASE LGATE PGND Q2 CHFOUT CBOUT CHSOC UGATE Q1 LOUT VOUT HSOC CF1 RCC VCC PVCC BOOT RHSOC CBOOT RBOOT DBOOT CHFIN CBIN
RDRV
ISL6540A
LSOC
RLSOC
RFS
CLSOC C2
ZFB C1 MARCTRL ROFS+ OFS+ FB
C3
R3 ZIN R1
R2
RMARG ROFSOFS-
VMON VCC VSEN+ SS
ROS
Rvmon1 VSENGND GND RvmonOS
CSS
4
FN6288.2 March 12, 2007
ISL6540A Typical Application III (Dual Data Rate I or II)
VDDQ 1.8V or 2.5V 5V RCC RVFF CVFF REN1 VFF EN REN2 CF4 UGATE 1K REFIN 15nF REFOUT 1K DIMM PG CPG_DLY PG_DLY FS PHASE CHFOUT LGATE PGND Q2 RLSOC CBOUT VIN CF2 CF1 VCC PVCC BOOT HSOC RHSOC CBOOT CHSOC Q1 LOUT VTT 1.25V (DDR I) 0.9V (DDR II) LIN DBOOT CHFIN CBIN
ISL6540A
LSOC
RFS
COMP
CLSOC C2
ZFB C1 MARCTRL ROFS+ OFS+ FB VMON RMARG ROFSVSEN+ OFSVSENSS CSS LINDRV GND GND
C3
R3
R2 R1
ZIN
RFB CSEN
5
FN6288.2 March 12, 2007
ISL6540A
Absolute Maximum Ratings
Input Voltage, VIN, VFF, HSOC . . . . . . . . . . . . . . . . -0.3V to +22.0V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V BOOT Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36V BOOT To PHASE Voltage (VBOOT-VPHASE). . . . . -0.3V to 7V (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 9V (<10ns) PHASE Voltage, VPHASE . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V . . . . . . . . . . . . . . . . . . . . . .VBOOT - 9V (<10ns) to VBOOT + 0.3V UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT VPHASE - 5V (<20ns Pulse Width, 10J) to VBOOT LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V GND - 2.5V (<20ns Pulse Width, 5J) to VCC + 0.3V Other Input or Output Voltages . . . . . . . . . . . . . -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Note 1, 2) JA (C/W) JC (C/W) QFN Package (Note 1, 2) . . . . . . . . . 32 5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300C
Recommended Operating Conditions
Input Voltage, VIN, VFF . . . . . . . . . . . . . . . . . . . . 3.3V to 20V 10% Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.5V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.5V Boot to Phase Voltage (Overcharged), VBOOT - VPHASE . . . . . .<6V Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40C to +85C Junction Temperature Range. . . . . . . . . . . . . . . . . .-40C to +125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. 2. JC, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details. 3. Test conditions identified as "GBD" are guaranteed by design simulation.
Electrical Specifications
SYMBOL INPUT SUPPLY CURRENTS IVCC IPVCC IVIN IVCC_S IPVCC_S IVIN_S
Recommended Operating Conditions, Unless Otherwise Noted TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER
Nominal VCC Supply Current Nominal PVCC Supply Current Nominal Vin Supply Current Shutdown VCC Supply Current Shutdown PVCC Supply Current Shutdown VIN Supply Current
VIN = VCC = PVCC = 5V, Fs = 600kHz, UGATE and LGATE Open VIN = VCC = PVCC = 5V; Fs = 600kHz, UGATE and LGATE Open VIN = VCC = PVCC = 5V; Fs = 600kHz, UGATE and LGATE Open EN = 0V, VCC = PVCC = VIN = 5V EN = 0V, VCC = PVCC = VIN = 5V EN = 0V, VCC = PVCC = VIN = 5V
-
8 3 0.5 3 1 0.5
13 4 1 4 2 1
mA mA mA mA mA mA
POWER-ON RESET PORVCC_R PORVCC_F PORVCC_H PORPVCC_R PORPVCC_F PORPVCC_H PORVFF_R PORVFF_F PORVFF_H Rising VCC Threshold Falling VCC Threshold VCC Hysterisis Rising PVCC Threshold Falling PVCC Threshold PVCC Hysterisis Rising VFF Threshold Falling VFF Threshold VFF Hysterisis 2.79 2.59 187 2.79 2.59 193 1.48 1.35 127 215 215 137 2.89 2.69 250 2.91 2.70 250 1.54 1.41 146 V V mV V V mV V V mV
6
FN6288.2 March 12, 2007
ISL6540A
Electrical Specifications
SYMBOL ENABLE VEN_REF IEN_HYS VEN OSCILLATOR OSCFMAX OSCFMIN OSC VOSC VOSC_MIN VFF PWM DMAX DMIN Maximum Duty Cycle Minimum Duty Cycle Leading and Trailing-edge Modulation Leading and Trailing-edge Modulation 100 0 % % Nominal Maximum Frequency Nominal Minimum Frequency Total Variation Ramp Amplitude Ramp Bottom Minimum Usable VFF Voltage VCC = 5V GBD GBD FS = 250kHz to 2MHz, VFF = 3.3V to 20V -17 2000 250 0.16*VFF 1.0 3.3 +17 kHz kHz % VP-P V V Input Reference Voltage Hysteresis Source Current Maximum Input Voltage 0.485 7.5 0.500 10 VCC + 0.3 0.515 11.5 V A V Recommended Operating Conditions, Unless Otherwise Noted (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER
REFERENCE TRACKING VREFIN VREFIN_OS IREFOUT VREFOUT Input Voltage Range External Reference Offset Maximum Drive Current Output Voltage Range VCC = 5V REFIN = 0.6V CL = 1F, VCC = 5V, REFOUT = 1.25V CL = 1F CL = 1F REFOUT = 1.25V REFOUT = 1.25V VCC = 5V 0.068 -1.8 0.01 -6 VCC - 0.6 0 19 1.0 VCC - 1.8V 2.2 VCC - 1.8V 11 VCC - 0.58 V mV mA V mV F V
VREFOUT_OS Maximum Output Voltage Offset CREFOUT_MIN Minimum Load Capacitance VREFIN_DIS REFERENCE VREF_COM VREF_IND VSYS_COM VSYS_IND ERROR AMPLIFIER DC Gain UGBW SR Unity Gain-Bandwidth Slew Rate System Accuracy Reference Voltage Input Disable Voltage
TA = 0C to +70C TA = -40C to +85C TA = 0C to +70C TA = -40C to +85C
0.587 0.585 -0.68 -1.0
0.591 0.591 -
0.595 0.597 0.68 1.0
V V % %
RL = 10k, CL = 100p, at COMP Pin RL = 10k, CL = 100p, at COMP Pin RL = 10k, CL = 100p, at COMP Pin
-
88 15 6
-
dB MHz V/s
DIFFERENTIAL AMPLIFIER UG UGBW SR DC Gain Unity Gain Bandwidth Slew Rate COMP = 10pF Standard Instrumentation Amplifier -1.9 0 20 10 0 6 VCC - 1.8 -0.2 VCC 1.9 dB MHz V/s mV A V V V
VOFFSET_IND Offset IVSENNegative Input Source Current Input Common Mode Range Max Input Common Mode Range Min VVSEN_DIS VSEN- Disable Voltage
INTERNAL LINEAR REGULATOR IVIN Maximum Current 200 mA
7
FN6288.2 March 12, 2007
ISL6540A
Electrical Specifications
SYMBOL RLIN
PVCC
Recommended Operating Conditions, Unless Otherwise Noted (Continued) TEST CONDITIONS MIN 5.42 TYP 2 5.50 1 0.05 MAX 3.9 5.71 UNITS V V/s V/s
PARAMETER
Saturated Equivalent Impedance VIN = 3.3V, Load = 100mA Linear Regulator Voltage VIN = 22V, Load = 0 to 100mA VIN = 0 V to 12V step, PVCC = 0 V VIN = 5.0 V to 12V step, PVCC = 5.0 V
VINDV/DT_Max Maximum Vin DV/DT
EXTERNAL LINEAR REGULATOR LIN_DRV Maximum Sinking Drive Current 3.2 5 6.4 mA
OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) DC Gain Drive Capability GATE DRIVERS RUGATE IUGATE RUGATE IUGATE RLGATE ILGATE RLGATE ILGATE Ugate Source Resistance 500mA Source Current, PVCC = 5.0V 1.0 2.0 1.0 2.0 1.0 2.0 0.4 4.0 A A A A CSS = 0.1F, at SS Pin CSS = 0.1F, at SS Pin 30 88 37 44 dB A
Ugate Source Saturation Current VUGATE-PHASE = 2.5V, PVCC = 5.0V Ugate Sink Resistance Ugate Sink Saturation Current Lgate Source Resistance Lgate Source Saturation Current Lgate Sink Resistance Lgate Sink Saturation Current 500mA Sink Current, PVCC = 5.0V VUGATE-PHASE = 2.5V, PVCC = 5.0V 500mA Source Current, PVCC = 5.0V VLGATE = 2.5V, PVCC = 5.0V 500mA Sink Current, PVCC = 5.0V VLGATE = 2.5V, PVCC = 5.0V
OVERCURRENT PROTECTION (OCP) ILSOC Low Side OCP (LSOC) Current Source LSOC = 0V to Vcc - 1.0V, TA = 0C to +70C LSOC = 0V to Vcc - 1.0V, TA = -40C to +85C Vcc = 2.9V and 5.6V TSAMPLE < 10s HSOC = 0.8V to 22V TA = 0C to +70C HSOC = 0.8V to 22V TA = -40C to +85C HSOC = 0.3V to 0.8V VCC = 2.9V and 5.5V TSAMPLE < 10s 86 84 91 89 84 100 100 2 100 100 2 107 109 106 107 107 A A mV A A A mV
ILSOC_OFSET LSOC Maximum Offset Error IHSOC High Side OCP (HSOC) Current Source
IHSOC_LOW IHSOC_OFSET HSOC Maximum Offset Error MARGINING CONTROL VMARG VMARG NMARG
MAR_CTRL MAR_CTRL MAR_CTRL
Minimum Margining Voltage of Internal Reference Maximum Margining Voltage of Internal Reference Margining Transfer Ratio Positive Margining Threshold Negative Margining Threshold Tri-state Input Level
RMARG = 10k, ROFS- = 6.01k, MAR_CRTL = 0V RMARG = 10k, ROFS+ = 6.01k, MAR_CRTL = VCC NMARG = (VOFS--VOFS+)/VMARG
-187 185 4.84 1.51 0.75
-197 197 5 1.8 0.9 1.325
-209 208 5.22 2.02 1.05 1.40
mV mV SDR V V V
Disable Mode
1.21
POWER GOOD MONITOR
VUVR VUVF VOVR VOVF TPG_DLY IPG_DLY VPG_DLY
Undervoltage Rising Trip Point Undervoltage Falling Trip Point Overvoltage Rising Trip Point Overvoltage Falling Trip Point PGOOD Delay PGOOD Delay Source Current PGOOD Delay Threshold Voltage CPG_DLY = 0.1F
-7% -13% 13% 7% 17 1.45
-9% -15% 15% 9% 7.1 21 1.49
-11% -17% 17% 11% 24 1.52
VSS VSS VSS VSS ms A V
8
FN6288.2 March 12, 2007
ISL6540A
Electrical Specifications
SYMBOL
IPG_LOW IPG_MAX VPG_MAX
Recommended Operating Conditions, Unless Otherwise Noted (Continued) TEST CONDITIONS IPGOOD = 5mA VPGOOD = 0.8V VCC = 3.3V MIN 23 TYP 6 MAX 0.150 UNITS V mA V
PARAMETER PGOOD Low Output Voltage Maximum Sinking Current Maximum Open Drain Voltage
Functional Pin Description
VSEN+ (Pin 1)
This pin provides differential remote sense for the ISL6540A. It is the positive input of a standard instrumentation amplifier topology with unity gain, and should connect to the positive rail of the load/processor. The voltage at this pin should be set equal to the internal system reference voltage (0.591V typical.)
OFS- (Pin 7)
This pin sets the negative margining offset voltage. Resistors should be connected to GND (ROFS-) and OFS+ (RMARG) from this pin. With MAR_CTRL logic low, the internal 0.591V reference is developed at the OFS- pin across resistor ROFS-. The voltage on OFS- is driven from OFS+ through RMARG. The resulting voltage differential between OFS+ and OFS- is divided by 5 and imposed on the system reference. The maximum designed offset of -1V between OFS+ and OFS- pins translates to a -200mV offset of the system reference.
VSEN- (Pin 2)
This pin provides differential remote sense for the regulator. It is the negative input of the instrumentation amplifier, and should connect to the negative rail of the load/processor. Typically 6A is sourced from this pin. The output of the remote sense buffer is disabled (High Impedance) by pulling VSEN- to VCC.
VCC (Pin 8, Analog Circuit Bias)
This pin provides power for the ISL6540A analog circuitry. The pin should be connected to a 2.9V to 5.5V bias through an RC filter from PVCC to prevent noise injection into the analog circuitry. This pin can be powered off the internal or external linear regulator options.
REFOUT (Pin 3)
This pin connects to the unmargined system reference through an internal buffer. It has a 19mA drive capability with an output common mode range of GND to VCC. The REFOUT buffer requires at least 1F of capacitive loading to be stable. This pin should not be left floating.
MARCTRL (Pin 9)
The MARCTRL pin controls margining function, a logic high enables positive margining, a logic low sets negative margining, a high impedance disables margining.
REFIN (Pin 4)
When the external reference pin (REFIN) is NOT within ~1.8V of VCC, the REFIN pin is used as the system reference instead of the internal 0.591V reference. The recommended REFIN input voltage range is ~68mV to VCC - 1.8V.
PG_DLY (Pin 10)
Provides the ability to delay the output of the PGOOD assertion by connecting a capacitor from this pin to GND. A 0.1F capacitor produces approximately a 7ms delay.
PGOOD (Pin 11)
Provides an open drain Power Good signal when the output is within 9% of nominal output regulation point with 6% hysteresis (15%/9%), and after soft-start is complete. PGOOD monitors the VMON pin.
SS (Pin 5)
This pin provides softstart functionality for the ISL6540A. A capacitor connected to ground along with the internal 37A Operational Transconductance Amplifier (OTA), sets the soft-start interval of the converter. This pin is directly connected to the non-inverting input of the error amplifier. To prevent noise injection into the error amplifier the SS capacitor should be located next to the SS and GND pins.
EN (Pin 12)
This pin is compared with an internal 0.50V reference and enables the soft-start cycle. This pin also can be used for voltage monitoring. A 10A current source to GND is active while the part is disabled, and is inactive when the part is enabled. This provides functionality for programmable hysteresis when the EN pin is used for voltage monitoring.
OFS+ (Pin 6)
This pin sets the positive margining offset voltage. Resistors should be connected to GND (ROFS+) and OFS- (RMARG) from this pin. With MAR_CTRL logic low, the internal 0.591V reference is developed at the OFS+ pin across resistor ROFS+. The voltage on OFS+ is driven from OFS- through RMARG. The resulting voltage differential between OFS+ and OFS- is divided by 5 and imposed on the system reference. The maximum designed offset of 1V between OFS+ and OFS- pins translates to a 200mV offset. 9
VFF (Pin 13)
The voltage at this pin is used for input voltage feed forward compensation and sets the internal oscillator ramp peak to peak amplitude at 0.16 * VFF. An external RC filter may be required at this pin in noisy input environments. The minimum recommended VFF voltage is 2.97V.
FN6288.2 March 12, 2007
ISL6540A
VIN (Pin 14, Internal Linear Regulator Input)
This pin should be tied directly to the input rail when using the internal or external linear regulator options. It provides power to the External/Internal linear drive circuitry. When used with an external 3.3V to 5V supply, this pin should be tied directly to PVCC. the bootstrap diode to prevent over charging of the BOOT capacitor during normal operation.
HSOC (Pin 22)
The high side sourcing current limit is set by connecting this pin with a resistor and capacitor to the drain of the high side MOSEFT. A 100A current source develops a voltage across the resistor which is then compared with the voltage developed across the high side MOSFET. An initial ~120ns blanking period is used to eliminate sampling error due to the switching noise before the current is measured.
LIN_DRV (Pin 15, External Linear Regulator Drive)
This pin allows the use of an external pass element to power the IC for input voltages above 5.0V. It should be connected to GND when using an external 5V supply or the internal linear regulator. When using the external linear regulator option, this pin should be connected to the gate of a PMOS pass element, a pull up resistor must be connected between the PMOS device's gate and source for proper operation.
LSOC (Pin 23)
The low side source and sinking current limit is set by placing a resistor (RLSOC) and capacitor between this pin and PGND. A 100A current source develops a voltage across RLSOC which is then compared with the voltage developed across the low side MOSFET when on. The sinking current limit is set at 1x of the nominal sourcing limit in ISL6540A. An initial ~120ns blanking period is used to eliminate the sampling error due to switching noise before the current is measured.
PVCC (Pin 16, Driver Bias Voltage)
This pin is the output of the internal series linear regulator. It also provides the bias for both low side and high side MOSFET drivers. The maximum voltage differential between PVCC and PGND is 6V. Its recommended operational voltage range is 2.9V to 5.5V. At minimum a 10F capacitor is required for decoupling PVCC to PGND. For proper operation the PVCC capacitor should be located next to the PVCC and the PGND pins and should be connected to these pins with dedicated traces.
FS (Pin 24)
This pin provides oscillator switching frequency adjustment by placing a resistor (RFS) from this pin to GND.
LGATE (Pin 17)
This pin provides the drive for the low side MOSFET and should be connected to its gate.
COMP (Pin 25)
This pin is the error amplifier output. It should be connected to the FB pin through the desired compensation network.
PGND (Pin 18, Power Ground)
This pin connects to the low side MOSFET's source and provides the ground return path for the lower MOSFET driver and internal power circuitries. In addition, PGND is the return path for the low side MOSFET's rDS(ON) current sensing circuit.
FB (Pin 26)
This pin is the inverting input of the error amplifier and has a maximum usable voltage of VCC - 1.8V. When using the internal differential remote sense functionality, this pin should be connected to VMON by a standard feedback network. In the event the remote sense buffer is disabled, the VMON pin should be connected to VOUT by a resistor divider along with FB's compensation network.
PHASE (Pin 19)
This pin connects to the source of the high side MOSFET and the drain of the low side MOSFET. This pin represents the return path for the high side gate driver. During normal switching, this pin is used for high side and low side current sensing.
GND (Pin 27, Analog Ground)
Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating.
VMON (Pin 28)
This pin is the output of the differential remote sense instrumentation amplifier. It is connected internally to the OV/UV/PGOOD comparators. The VMON pin should be connected to the FB pin by a standard feedback network. In the event of the remote sense buffer is disabled, the VMON pin should be connected to VOUT by a resistor divider along with FB's compensation network. An RC filter should be used if VMON is to be connected directly to FB instead of to VOUT through a separate resistor divider network.
UGATE (Pin 20)
This pin provides the drive for the high side MOSFET and should be connected to its gate.
BOOT (Pin 21)
This pin provides the bootstrap bias for the high side driver. The absolute maximum voltage differential between BOOT and PHASE is 6.0V (including the voltage added due to the overcharging of the bootstrap capacitor); its operational voltage range is 2.5V to 5.5V with respect to PHASE. It is recommended that a 2.2 resistor be placed in series with
GND (Bottom Side Pad, Analog Ground)
Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating.
FN6288.2 March 12, 2007
10
ISL6540A Functional Description
Initialization
The ISL6540A automatically initializes upon receipt of power without requiring any special sequencing of the input supplies. The Power-On Reset (POR) function continually
HIGH = ABOVE POR; LOW = BELOW POR
VCC POR VFF POR PVCC POR EN POR AND SOFT-START
FIGURE 1. SOFT-START INITIALIZATION LOGIC
monitors the input supply voltages (PVCC, VFF, VCC) and the voltage at the EN pin. Assuming the EN pin is pulled to above ~0.50V, the POR function initiates soft-start operation after all input supplies exceed their POR thresholds.
VIN RUP
continues to charge the SS pin until the voltage on COMP exceeds the bottom of the oscillator ramp, at which point, the driver outputs are enabled, with the low side MOSFET first being held low for 200ns to provide for charging of the bootstrap capacitor. Once the driver outputs are enabled, the OTA's target voltage is then changed to the margined (if margining is being used) reference voltage (VREF_MARG), and the SS pin is ramped up or down accordingly. This method reduces startup surge currents due to a pre-charged output by inhibiting regulator switching until the control loop enters its linear region. By ramping the positive input of the error amplifier to VCC and then to VREF_MARG, it is even possible to mitigate surge currents from outputs that are pre-charged above the set output voltage. As the SS pin connects directly to the non-inverting input of the error amplifier, noise on this pin should be kept to a minimum through careful routing and part placement. To prevent noise injection into the error amplifier the SS capacitor should be located within 150 mils of the SS and GND pins. Soft-start is declared done when the drivers have been enabled and the SS pin is within 3mV of VREF_MARG.
VMON
VREF
Sys_Enable
+15% +9%
RDOWN IEN_HYS=10A
VREF_MARG
V EN_HYS R UP = ------------------------I EN_HYS R UP * V EN_REF R DOWN = -------------------------------------------------------V EN_FTH - V EN_REF V EN_FTH = V EN_RTH - V EN_HYS FIGURE 2. ENABLE POR CIRCUIT
UV
-9% -15%
GOOD OV
GOOD UV
FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW 1.49V T PG_DLY = C PG_DLY --------------21A
With all input supplies above their POR thresholds, driving the EN pin above 0.50V initiates a soft-start cycle. In addition to normal TTL logic, the enable pin can be used as a voltage monitor with programmable hysteresis through the use of the internal 10A sink current and an external resistor divider. This feature is especially designed for applications that have input rails greater than a 3.3V and require a specific input rail POR and Hysteresis levels for better undervoltage protection. Consider for a 12V application choosing RUP = 100k and RDOWN = 5.76k there by setting the rising threshold (VEN_RTH) to ~10V and the falling threshold (VEN_FTH) to ~9V, for 1V of hysteresis (VEN_HYS). Care should be taken to prevent the voltage at the EN pin from exceeding VCC when using the programmable UVLO functionality.
Power Good
The power good comparator references the voltage on the soft-start pin to prevent accidental tripping during margining. The trip points are shown on Figure 3. Additionally, power good will not be asserted until after the completion of the soft-start cycle. A 0.1F capacitor at the PG_DLY pin will add an additional ~7ms delay to the assertion of power good. PG_DLY does not delay the de-assertion of power good.
Under and Overvoltage Protection
The Undervoltage (UV) and Overvoltage (OV) protection circuitry compares the voltage on the VMON pin with the reference that tracks with the margining circuitry to prevent accidental tripping. UV and OV functionality is not enabled until the end of soft-start.
Soft-Start
The POR function activates the internal 37A OTA which begins charging the external capacitor (CSS) on the SS pin to a target voltage of VCC. The ISL6540A's soft-start logic
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An OV event is detected asynchronously and causes the high side MOSFET to turn off, the low side MOSFET to turn on (effectively a 0% duty cycle), and PGOOD to pull low. The regulator stays in this state and overrides sourcing and sinking OCP protections until the OV event is cleared. An UV event is detected asynchronously and results in the PGOOD pulling low. smooth the voltage across RHSOC in the presence of switching noise on the input bus. Simple Low Side OCP Equation
I OC_SOURCE * r DS ( ON )LowSide R LSOC = -------------------------------------------------------------------------------------100A
Detailed Low Side OCP Equations
I I + ---- * r OC_SOURCE 2 DS ( ON ),L R LSOC = ------------------------------------------------------------------------------------I LSOC * N L V IN - V OUT V OUT I = ------------------------------- * --------------FS L V IN I LSOC * N L * R LSOC I I OC_SINK = ------------------------------------------------------- - ---2 r DS ( ON ),L N L = Number of low side MOSFETs
Overcurrent Protection
The ISL6540A monitors both the high side MOSFET and low side MOSFET for overcurrent events. Dual sensing allows the ISL6540A to detect overcurrent faults at the very low and very high duty cycles that can result from the ISL6540A's wide input range. The OCP function is enabled with the drivers at startup and detects the peak current during each sensing period. A resistor and a capacitor between the LSOC pin and GND set the low side source and sinking current limits. A 100A current source develops a voltage across the resistor which is then compared with the voltage developed across the low side MOSFET at conduction mode. The measurement comparator uses offset correcting circuitry to provide precise current measurements with roughly 2mV of offset error. An ~120ns blanking period, implemented on the upper and lower MOSFET current sensing circuitries, is used to reduce the current sampling error due to the leading-edge switching noise. An additional 120ns low pass filter is used to further reduce measurement error due to noise. In sourcing current applications, the LSOC voltage is inverted and compared with the voltage across the MOSFET while on. When this voltage exceeds the LSOC set voltage, a sourcing OCP fault is triggered. A 1000pF or greater filter capacitor should be used in parallel with RLSOC to prevent on chip parasitics from impacting the accuracy of the OCP measurement. The ISL6540A's sinking current limit is set to the same voltage as its sourcing limit. In sinking applications, when the voltage across the MOSFET is greater than the voltage developed across the resistor (RLSOC) a sinking OCP event is triggered. To avoid non-synchronous operation at light load, the peak to peak output inductor ripple current should not be greater than twice of the sinking current limit. The high side sourcing current limit is set by connecting the HSOC pin with a resistor (RHSOC) and a capacitor to the drain of the high side MOSEFT. A 100A current source develops a voltage across the resistor which is then compared with the voltage developed across the high side MOSFET while on. When the voltage drop across the MOSFET exceeds the voltage drop across the resistor, a sourcing OCP event occurs. A 1000pF or greater filter capacitor should be used in parallel with RHSOC to prevent on chip parasitics from impacting the accuracy of the OCP measurement and to
Sourcing OCP faults cause the regulator to disable (Ugate and Lgate drives pulled low, PGOOD pulled low, soft-start capacitor discharged) itself for a fixed period of time after which a normal soft-start sequence is initiated. The period of time the regulator waits before attempting a soft-start sequence is set by three charge and discharge cycles of the soft-start capacitor. Simple High Side OCP Equation
I OC_SOURCE * r DS ( ON )HighSide R HSOC = ---------------------------------------------------------------------------------------100A
Detailed High Side OCP Equation
I I + ---- * r OC_SOURCE 2 DS ( ON ),U R HSOC = -------------------------------------------------------------------------------------I HSOC * N U N U = Number of high side MOSFETs
Sinking OCP faults cause the low side MOSFET drive to be disabled, effectively operating the ISL6540A in a non-synchronous manner. The fault is maintained for three clock cycles at which point it is cleared and normal operation is restored. OVP fault implementation overrides sourcing and sinking OCP events, immediately turning on the low side MOSFET and turning off the high side MOSFET. The OC trip point varies mainly due to the MOSFETs rDS(ON) variations and system noise. To avoid overcurrent tripping in the normal operating load range, find the RHSOC and/or RLSOC resistor from the previous detailed equations with: 1. Maximum rDS(ON) at the highest junction temperature. 2. Minimum ILSOC and/or IHSOC from specification table. 3. Determine the overcurrent trip point greater than the maximum output continuous current at maximum inductor ripple current.
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Frequency Programming
By tying a resistor to GND from FS pin, the switching frequency can be set between 250kHz and 2MHz. (VIN) can range between 3.3V to 20V 10%. The internal linear regulator is to provide power for both the internal MOSFET drivers through the PVCC pin and the analog circuitry through the VCC pin. The VCC pin should be connected to the PVCC pin with an RC filter to prevent high frequency driver switching noise from entering the analog circuitry. When VIN drops below 5.5V, the pass element will saturate; PVCC will track VIN, minus the dropout of the linear regulator: PVCC = VIN-2xIVIN. When used with an external 5V supply, the VIN pin should be tied directly to PVCC. At startup (PVCC = 0V and Vin = 0V) the DV/DT on VIN should be kept below 1V/s to prevent electrical overstress on PVCC. Care should be taken to keep the DV/DT on Vin below 0.05V/s if the initial steady state voltage on PVCC is between 2.0V and 5.5V, as electrical overstress on PVCC is otherwise possible.
Oscillator/VFF
The Oscillator is a triangle waveform, providing for leading and falling edge modulation. The bottom of the oscillator waveform is set at 1.0V. The ramp's peak to peak amplitude is determined from the voltage on the VFF (Voltage Feed Forward) pin by the equation: Vosc = 0.16*VFF. An internal RC filter of 233k and 2pF (341kHz) provides filtering of the VFF voltage. An external RC filter may be required to augment this filter in the event that it is insufficient to prevent noise injection or control loop interactions. Voltages below 2.9V on the VFF pin may result in undesirable operation due to extremely small peak to peak oscillator waveforms. The oscillator waveform should not exceed VCC -1.0V. For high VFF voltages the internal/external 5.5V linear regulator should be used. 5.5V on VCC provides sufficient headroom for 100% duty cycle operation when using the maximum VFF voltage of 22V. In the event of sustained 100% duty cycle operation, defined as 32 clock cycles where no LG pulse is detected, LG will be pulsed on to refresh the design's bootstrap capacitor.
100
External Series Linear Regulator
The LIN_DRV pin provides sinking drive capability for an external pass element linear regulator controller. The external linear options are especially useful when the internal linear dropout is too large for a given application. When using the external linear regulator option, the LIN_DRV pin should be connected to the gate of a PMOS device, and a resistor should be connected between its gate and source. A resistor and a capacitor should be connected from gate to source to compensate the control loop. A PNP device can be used instead of a PMOS device in which case the LIN_DRV pin should be connected to the base of the PNP pass element. The sinking capability of the LIN_DRV pin is 5mA, and should not be exceeded if using an external resistor for a PMOS device. The designer should take care in designing a stable system when using external pass elements. The VCC pin should be connected to the PVCC pin with an RC filter to prevent high frequency driver switching noise from entering the analog circuitry.
RESISTANCE (k)
10
1 100
1000
10000
FREQUENCY (kHz) FIGURE 4. RFS RESISTANCE vs FREQUENCY
High Speed MOSFET Gate Driver
The integrated driver has similar drive capability and features to Intersil's ISL6605 stand alone gate driver. The PWM tri-state feature helps prevent a negative transient on the output voltage when the output is being shut down. This eliminates the schottky diode that is used in some systems for protecting the microprocessor from reversed-outputvoltage damage. See the ISL6605 datasheet for specification parameters that are not defined in the current ISL6540A electrical specifications table. A 1-2 resistor is recommended to be in series with the bootstrap diode when using VCCs above 5.0V to prevent the bootstrap capacitor from overcharging due to the negative swing of the trailing edge of the phase node.
Fs [ Hz ] 1.178 x10
10
* RT [ ]
- 0.973
(R T TO GND)
Internal Series Linear Regulator
The VIN pin is connected to PVCC with a 2 internal series linear regulator, which is internally compensated. The external series linear regulator option should be used for applications requiring pass elements of less than 2. When using the internal regulator, the LIN_DRV pin should be connected directly to GND. The PVCC and VIN pins should have a bypasses capacitor (at least 10F on PVCC is required) connected to PGND. For proper operation the PVCC capacitor must be within 150 mils of the PVCC and the PGND pins, and be connected to these pins with dedicated traces. The internal series linear regulator's input 13
Margining Control
When the MAR_CTRL is pulled high or low, the positive or negative margining functionality is respectively enabled.
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When MAR_CTRL is left floating, the function is disabled. Upon UP margining, an internal buffer drives the OFS- pin from VCC to maintain OFS+ at 0.591V. The resistor divider, RMARG and ROFS+, causes the voltage at OFS- to be increased. Similarly, upon DOWN margining, an internal buffer drives the OFS+ pin from VCC to maintain OFS- at 0.591V. The resistor divider, RMARG and ROFS-, causes the voltage at OFS+ to be increased. In both modes the voltage difference between OFS+ and OFS- is then sensed with an instrumentation amplifier and is converted to the desired margining voltage by a 5:1 ratio. The maximum designed margining range of the ISL6540A is 200mV, this sets the MINIMUM value of ROFS+ or ROFS- at approximately 5.9K for an RMARG of 10K for a MAXIMUM of 1V across RMARG. The OFS pins are completely independent and can be set to different margining levels. The maximum usable reference voltage for the ISL6540A is VCC-1.8V, and should not be exceeded when using the margining functionality, i.e, VREF_MARG < VCC - 1.8V.
V REF R MARG V MARG_UP = -------------- * -------------------5 R OFS+ V REF R MARG V MARG_DOWN = -------------- * -------------------5 R OFS-
VCC REFERENCE VREF=0.591V ISL6540A STATE MACHINE
REFIN 800mV
REFOUT
MARGINING BLOCK
VREF_MARG
OTA
FIGURE 5. SIMPLIFIED REFERENCE BUFFER
Internal Reference and System Accuracy
The internal reference is trimmed to 0.591V. The total DC system accuracy of the system is within 0.68% over commercial temperature range, and 1.00% over industrial temperature range. System accuracy includes error amplifier offset, OTA error, and bandgap error. Differential remote sense offset error is not included. As a result, if the differential remote sense is used, then an extra 1.9mV of offset error enters the system. The use of REFIN may add up to 2.2mV of additional offset error.
An alternative calculation provides for a desired percentage change in the output voltage when using the internal 0.591V reference:
R MARG V PCT_UP = 20 * -------------------R OFS+ R MARG V pct_DOWN = 20 * -------------------R OFS-
Differential Remote Sense Buffer
The differential remote sense buffer is essentially an instrumentation amplifier with unity gain. The offset is trimmed to 1.5mV for high system accuracy. As with any instrumentation amplifier typically 6A are sourced from the VSEN- pin. The output of the remote sense buffer is connected directly to the internal OV/UV comparator. As a result, a resistor divider should be placed on the input of the buffer for proper regulation, as shown in Figure 6. The VMON pin should be connected to the FB pin by a standard feed-back network. A small capacitor, CSEN in Figure 6, can be added to filter out noise, typically CSEN is chosen so the corresponding time constant does not reduce the overall phase margin of the design, typically this is 2x to 10x switching frequency of the regulator. As some applications will not use the differential remote sense, the output of the remote sense buffer can be disabled (high impedance) by pulling VSEN- within 1.8V of VCC. As the VMON pin is connected internally to the OV/UV/PGOOD comparator, an external resistor divider must then be connected to VMON to provide correct voltage information for the OV/UV comparator. An RC filter should be used if VMON is to be connected directly to FB instead of to VOUT through a separate resistor divider network. This filter prevents noise injection from disturbing the OV/UV/PGOOD comparators on VMON. VMON may also be connected to the SS pin, which completely bypasses the OV/UV/PGOOD functionality.
When not used in a design OFS+, OFS-, and MARCTRL should be left floating. To prevent damage to the part, OFS+ and OFS- should not be tied to VCC or PVCC.
Reference Output Buffer
The internal buffer's output tracks the unmargined system reference. It has a 19mA drive capability, with maximum and minimum output voltage capabilities of VCC and GND respectively. Its capacitive loading can range from 1F to above 17.6F, which is designed for 1 to 8 DIMM systems in DDR (Dual Data Rate) applications. 1F of capacitance should always be present on REFOUT. It is not designed to drive a resistive load and any such load added to the system should be kept above 300k total impedance. The Reference Output Buffer should not be left floating.
Reference Input
The REFIN pin allows the user to bypass the internal 0.591V reference with an external reference. Asynchronously if REFIN is NOT within ~1.8V of VCC, the external reference pin is used as the control reference instead of the internal 0.591V reference. The minimum usable REFIN voltage is ~68mV while the maximum is VCC - 1.8V - VMARG (if present).
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VSENSE(REMOTE) VOUT (LOCAL) 10 VSENSE+ (REMOTE)
GND (LOCAL)
10 ROS CSEN
RFB
ZIN VSEN+ VMON FB
ZFB COMP
VCC
VSEN-
1.8V GAIN=1 VSS
OV/UV COMP
ERROR AMP
FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding.
VIN
components shown in Figure 8 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the ISL6540A within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs' gate and source connections from the ISL6540A must be sized to handle up to 4A peak current.
BOOT CBOOT +VIN D1 Q1 LO VOUT LOAD
FN6288.2 March 12, 2007
SS
ISL6540A
PHASE +5V PVCC Q2 CO
ISL6540A
UGATE PHASE CIN LGATE PGND Q2 Q1 LO
CSS GND
CPVCC PGND
VOUT
CO
LOAD
FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES
RETURN
FIGURE 7. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS
Proper grounding of the IC is important for correct operation in noisy environments. The PGND pin should be connected to board ground at the source of the low side MOSFET with a wide short trace. The GND pin should be connected to a large copper fill under the IC which is subsequently connected to board ground at a quite location on the board, typically found at an input or output bulk (electrolytic) capacitor. Figure 8 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage
Figure 7 shows the critical power components of the converter. To minimize the voltage overshoot/undershoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The
15
ISL6540A
current paths on the SS pin and locate the capacitor, CSS close to the SS pin (as described earlier) as the internal current source is only 37A. Provide local decoupling between PVCC and PGND pins as described earlier. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figures 9 and 10. Use the following guidelines for locating the poles and zeros of the compensation network:
C2
Compensating the Converter
The ISL6540A single-phase converter is a voltage-mode controller. This section highlights the design considerations for a voltage-mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended (see Figure 9).
C2 R2 C1
COMP
R2 -
C1
R3
C3
FB E/A + VREF VMON + VSENVSEN+
R1
RFB CSEN ROS
COMP FB OSCILLATOR
C3 R3 R1
VOUT VIN
ISL6540A
VMON PWM CIRCUIT
VOSC L
UGATE
DCR
FIGURE 9. COMPENSATION CONFIGURATION FOR ISL6540A WHEN USING DIFFERENTIAL REMOTE SENSE
HALF-BRIDGE DRIVE
PHASE
C ESR
Figure 10 highlights the voltage-mode control loop for a synchronous-rectified buck converter, when using an internal differential remote sense amplifier. The output voltage (VOUT) is regulated to the reference voltage, VREF, level. The error amplifier output (COMP pin voltage) is compared with the oscillator (OSC) triangle wave to provide a pulse-width modulated wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and C). The output filter capacitor bank's equivalent series resistance is represented by the series resistor ESR. The modulator transfer function is the small-signal transfer function of VOUT /VCOMP. This function is dominated by a DC gain, given by DMAXVIN /VOSC, and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE . For the purpose of this analysis C and ESR represent the total output capacitance and its equivalent series resistance.
1 F LC = --------------------------2 L C 1 F CE = -------------------------------2 C ESR
LGATE
ISL6540A
EXTERNAL CIRCUIT
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
1. Select a value for R1 (1k to 10k, typically). Calculate value for R2 for desired converter bandwidth (F0). If setting the output voltage to be equal to the reference set voltage as shown in Figure 9, the design procedure can be followed as presented. However, when setting the output voltage via a resistor divider placed at the input of the differential amplifier (as shown in Figure 10), in order to compensate for the attenuation introduced by the resistor divider, the below obtained R2 value needs be multiplied by a factor of (ROS+RFB)/ROS. The remainder of the calculations remain unchanged, as long as the compensated R2 value is used.
V OSC R 1 F 0 R 2 = -------------------------------------------d MAX V IN F LC
The compensation network consists of the error amplifier (internal to the ISL6540A) and the external R1-R3, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase margin (better than 45). Phase margin is the difference between the closed loop phase at F0dB and 180. The equations that follow relate the compensation network's 16
A small capacitor, CSEN in Figure 10, can be added to filter out noise, typically CSEN is chosen so the corresponding time constant does not reduce the overall phase margin of the design, typically this is 2x to 10x switching frequency of the regulator. As the ISL6540A supports 100% duty cycle, dMAX equals 1. The ISL6540A also uses feedforward compensation, as such VOSC is equal
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to 0.16 multiplied by the voltage at the VFF pin. When tieing VFF to VIN the above equation simplifies to:
0.16 R 1 F 0 R 2 = ---------------------------------F LC
peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop
1 F Z1 = -----------------------------2 R 2 C 1 1 F Z2 = ------------------------------------------------2 ( R 1 + R 3 ) C 3 1 F P1 = -------------------------------------------C1 C2 2 R 2 -------------------C1 + C2 1 F P2 = -----------------------------2 R 3 C 3
2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 frequency (to maximize phase boost at FLC).
1 C 1 = ---------------------------------------------2 R 2 0.5 F LC
3. Calculate C2 such that FP1 is placed at FCE.
C1 C 2 = ------------------------------------------------------2 R 2 C 1 F CE - 1
4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below FSW (typically, 0.5 to 1.0 times FSW). FSW represents the regulator's switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter.
R1 R 3 = --------------------F SW ----------- - 1 F LC 1 C 3 = -----------------------------------------------2 R 3 0.7 F SW
error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 against the capabilities of the error amplifier. The closed loop gain, GCL, is constructed on the log-log graph of Figure 11 by adding the modulator gain, GMOD (in dB), to the feedback compensation gain, GFB (in dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain.
FZ1 FZ2 GAIN FP1 FP2 MODULATOR GAIN COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP E/A GAIN
R2 20 log ------- R1 0
D MAX V IN 20 log ---------------------------------V OSC
GFB GCL
It is recommended that a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier's open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the
D MAX V IN 1 + s ( f ) ESR C G MOD ( f ) = ------------------------------ ---------------------------------------------------------------------------------------------------------2 V OSC 1 + s ( f ) ( ESR + DCR ) C + s ( f ) L C 1 + s ( f ) R2 C1 G FB ( f ) = --------------------------------------------------- s ( f ) R1 ( C1 + C2 ) 1 + s ( f ) ( R1 + R3 ) C3 ----------------------------------------------------------------------------------------------------------------------- C1 C2 ( 1 + s ( f ) R 3 C 3 ) 1 + s ( f ) R 2 -------------------- C 1 + C 2 G CL ( f ) = G MOD ( f ) G FB ( f ) where, s ( f ) = 2 f j
LOG
GMOD LOG FLC FCE F0 FREQUENCY
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a -20dB/decade slope and a phase margin greater than 45. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, FSW.
frequency response of the modulator (GMOD), feedback compensation (GFB) and closed-loop response (GCL): As before when tieing VFF to VIN terms in the above equations can be simplified as follows:
1 V IN D MAX V IN ------------------------------ = -------------------------- = 6.25 V OSC 0.16 V IN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout.
COMPENSATION BREAK FREQUENCY EQUATIONS Figure 11 shows an asymptotic plot of the DC/DC converter's gain vs. frequency. The actual modulator gain has a high gain 17
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Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1.0F ceramic capacitors in the 1206 surface-mount package. Follow on specifications have only increased the number and quality of required ceramic decoupling capacitors. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
L O x I TRAN t RISE = ------------------------------V IN - V OUT L O x I TRAN t FALL = -----------------------------V OUT
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a lower input source such as 1.8V or 3.3V, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximated below.
I IN, RMS =
OR
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:
V IN - V OUT V OUT I = ------------------------------- * --------------FS x L V IN V OUT = I x ESR
I 2 2 I O ( D - D 2 ) + ------- D 12
VO D = ---------VIN
I IN, RMS = K ICM * I O
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6540A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient
For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from
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FN6288.2 March 12, 2007
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0.60 0.50
0.5Io
MOSFET Selection/Considerations
The ISL6540A requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). The upper MOSFET exhibits turn-on and turn-off switching losses as well as the reverse recover loss, while the synchronous rectifier exhibits body-diode conduction losses during the leading and trailing edge dead times.
I 2 r DS ( ON ),L P LOWER = I O 2 + ------- * -------------------------- * ( 1 - D ) + P DEAD N 12
L
0.40
KICM
0.30
0.25Io
0.20
I=0Io
0.10 0.00 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
DUTY CYCLE (D)
0.8 0.9
1
FIGURE 12. INPUT-CAPACITOR CURRENT MULTIPLIER FOR SINGLE-PHASE BUCK CONVERTER
AVX, and the 593D series from Sprague are both surge current tested.
I I P DEAD = I O + ----- * V DT * t DT + I O - ----- * V DL * t DL * F S 12 12 I 2 r DS ( ON ),U P UPPER = I O 2 + ------- * --------------------------- * D + P SW + P Qrr N 12
U
I I P SW = I O + ----- * t OFF + I O - ----- * t ON * VIN * F S 12 12 P Qrr = Q rr * VIN * F S
where D is the duty cycle = VO/VIN; Qrr is the reverse recover charge; tDLand tDT are leading and trailing edge dead time, and tON & tOFF are the switching intervals. These equations do not include the gate-charge losses that are proportional to the total gate charge and the switching frequency and partially dissipated by the internal gate resistance of the MOSFETs. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
ISL6540A DC/DC Converter Application Circuit
Detailed information on the application circuit, including a complete Bill-of-Materials and circuit board description, can be found in application note AN1253. See Intersil's home page on the web: http://www.intersil.com.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN6288.2 March 12, 2007
ISL6540A Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
2X 0.15 C A A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X C 0.08 C SEATING PLANE SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 0 TOP VIEW A2 A / / 0.10 C B E/2 E 2X 0.15 C B D D/2
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P 0.20 0.50 2.95 2.95 0.18 MIN 0.80 NOMINAL 0.90 0.02 0.65 0.20 REF 0.25 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.50 BSC 0.60 28 7 7 0.60 12 0.75 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 2 3 3 9 9 Rev. 1 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
9
9 CORNER OPTION 4X
C L
SECTION "C-C" C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.
L1 e CC
10
L L1 e
10
L
TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
20
FN6288.2 March 12, 2007

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